The semiconductor industry continues to progress by providing the potential to place increasingly large numbers of devices or logic gates on a chip at an average rate approaching doubling each year. Similarly, chip packaging technologies are developing which dramatically increase the density of chips which can be packed in the various physical packaging modules. These effects produce a continuous flow of improved system implementation possibilities which are so dramatic that they are difficult to relate or compare to previous designs and design methodologies.
Unfortunately these new technologies require a continuous flow of improved design techniques and designer tools in order to attack the various complexity management problems they bring along. Specifically, design verification, physical layout and interconnection and test generation must be performed on the chips and other physical modules. It has been determined analytically and empirically that the magnitude of these tasks grows about exponentially with the number of devices per chip or module. The present invention relates to the design verification portion of the problem.
When considering the problem of verifying the design of a single LSI or VLSI chip, there are two analogies that can be drawn. The first is fairly obvious and relates to the problem of verifying a complete central processor unit or CPU to that of verifying a chip. Verification of a new design of complexity containing about 100,000 logic gates is a known task. The smaller Control Data Corporation CYBER 170 machines are of this design magnitude. The verification process consists of running thousands of lines of diagnostic software followed by the machine's operating system processing real application software. The result of this verification is typically a list of design changes which can easily number in the hundreds.
People are currently designing 32 bit CPU chips, using today's processing technology, which are within half this complexity. Verification of these chips is done using a simulator computer program, which emulates as closely as possible the detailed operation of these chips in an attempt to uncover design problems before the chips are fabricated. It seems that the number of test cases required to verify the single chip CPU must approach that which was run on complete computer designs of nearly the same complexity if an equivalent level of verification is to be obtained.
A computer alogorithm is presently in use as a high performance simulator and which provides error free designs at a rate of 9 good designs per 10 chips. At this point, the second analogy can be drawn which relates the verification problem to that of the physical silicon chip processing yield. For a given maufacturing process, there is a given statistical fault density, as stated in faults per unit area. The yield of a chip with a given area is a complex formula, but a primary effect is that the ratio of faulty chips to total chips per silicon wafer grows exponentially with chip area. The design "process" currently produces a "yield" of 90 percent of an "area" of 250 gates per chip. Using the same design "process" and increasing the "area" to 5000 gates results in a "yield" that approaches zero. This implies that the design process which relies heavily on the use of the simulator is in need of dramatic improvement if we wish to deal effectively with chips of this complexity. Analogies are seldom totally accurate, but even if they are only partially correct, the effects predicted are rather severe.
The current state of the art in simulation technology allows logic simulation to operate at a rate of 90,000 logical switching events per second. At this rate, it would take several days of continuous simulation execution to simulate one second of real activity in a modest sized CPU. Furthermore, this simulation requires a very large computer system to execute at this rate. Such a system is expensive and rather inconvenient to use due to the batch execution environment of the simulator program and the commonly required sharing of the computer resource. This inconvenience is often underrated, because people have learned to accept it, seeing no other options. It is believed that this has a significant affect on design time and designer creativity in the real world.
Simulator execution rate is the major technical challenge due to the need to run very large numbers of test cases for final verification of logic network or chip design and to allow an interactive response rate for the same computer for smaller jobs at the same time. A truely interactive response would allow a simulator system to be used as a design optimization tool if coupled to a graphic logic entry system.
Problems also exist in trying to apply simulators developed for bipolar semiconductor technologies to the new MOS technologies. These simulators tend to be short on features needed for MOS. A list of desirable features for MOS simulation is listed below along with the ability of current Control Data Corporation simulation systems to handle them:
______________________________________ SYSTEM FEATURE ASSIST LSISIM AFS ______________________________________ Rise & Fall Delay Yes No No Bi-directional Signals Yes No No Device Level Simulation Limited No No Device Level Fault Models -- -- No ______________________________________
Device level simulation is the ability to model individual transistors (NMOS, PMOS, GAAS) and resistors to provide complete and final verification of design and interconnection routing and to provide the flexibility needed for full custom designed technologies. Additional simulation states are needed to model transistors. Also, each state must carry a relative strength factor to allow dynamic charge effects, pull-ups and variable device sizes to be modeled.